CHISEL based Multi-stage RISC-V CPU Construction and Performance Evaluation with Synthesis Constraints

Abstract

The rapid proliferation of embedded systems, computer happened in the last five decades since 1960 due to the advancement of design and manufacture of microelectronic devices. Since then, various architectures have been explored continuously to find the more cost-effective, energy efficient solution. One of the major stumbling blocks of accelerating the innovation of architectures as the companies protected their of being publicly available.

The open-source movement in the context of electronic hardware design started almost after a decade. Since then, many open-source architectures have been developed by enthusiasts and collaborative communities. Some of the projects are OpenSPARC, Amber, OpenRISC, S1 Core, OpenPiton. In 2010, previous inventors of RISC, new open ISA were released in the name of RISC-V. The movement not only makes the devices with the architecture inexpensive but also will pave the way for the designers and programmers to explore the hardware specifications to optimize the software-defined solutions. The industry standard HDL languages like VHDL is in the fourth decade since released by DoD. Designing computers with high-level object-oriented functional languages will not-only reduce the time in research and development but also enable traditional programmers to contribute to the open-source projects. Chisel is a tool that is designed to construct electronic hardware based on Scala programming language. Open-source architecture project is driven by Berkeley and tooling (Chisel/FIRRTL) facilitates sufficient support for diving into further research extensions experiments related to RISC-V. In this thesis, the study and implementation of a pipelined RISC-V CPU are performed. The goal was to make the design lighter, simpler and less-sophisticated for small embedded system applications. To simplify architecture, the control and status registers are not included in the design.To test and verify the various smaller constituent modules testbenches are also designed using Chisel. The Verilog file generated after the compilation is used for RTL synthesis using CAD software. After successful completion of steps of hardware synthesis phase, necessary data are extracted for further analysis in terms of area, power and timing. Leakage power and dynamic power consumption of each respective module and the overall power dissipation are investigated. Total number of cells, cell area and number of gates are generated by the CAD software. Timing violations and the rate of increase of the chip area are also measured in various operating frequency range.