A Thermal Model for Integrated Circuits (ICs) for Power Delivery Estimation for Realistic Power Map Including the Hot Spots

Abstract

Thermal behavior of integrated circuits (IC) is usually represented by IC thermal models. Such model is the simplification of the detailed IC package, and its main use case is in electronic design. IC thermal models help in prediction and analyzation of heat dissipation within an IC and its surrounding environment. Heat dissipation inside an IC drives the temperature within it which has a direct effect on its performance reliability and efficiency. Though some heat dissipation is expected, more than optimum amount will adversely affect the performance and power consumption of the designed IC. Hence, it is crucial to study the thermal characteristics of ICs for estimating their lifespan and efficiency. IC thermal models and related simulations are utilized for power mapping and packaging in the design process. In practice, thermal models are available at the later stages of IC development process. However, by then, it is already too late to modify the design and optimize it. But thermal models and simulation can be used to find out the potential thermal challenges during the conceptual and early design phases in System-on-Chip (SoC) development. This will allow the research teams to address the thermal issues before they become a critical problem. A realistic thermal model can give a holistic view of the thermal landscape which would help both SoC R&D (Research and Development) and BTS (Base Transceiver Station) unit PD (Product Development) teams to take informed decisions jointly to address present and upcoming thermal challenges. This will also help to validate proposed thermal solutions and strategies and encourage engineers to take the most effective thermal management techniques. This will, eventually, be cost-effective and save a lot of resources. The aim of this thesis is to provide a realistic and accurate power map of the package through systemlevel simulations at various stages, especially at the earlier phases, of the chip design process. The objectives include proposing a model to enhance the fidelity and reliability of the system-level simulations by considering various scenarios. The research is carried out in two phases. Initially, a thermal model is proposed based on worst-case scenarios. As the research moves ahead, alternatives are explored, and the model is improved gradually. Finally, an accurate thermal model for power delivery is proposed to provide a realistic power map including the hot spots and fine-tuning the thermal model for specific user cases. This thesis explores different IC designs for finding out realistic power mapping and packaging techniques through system-level simulations. It aims at providing practical methodologies at various stages of IC design process through implementation of proposed thermal model. The proposed model provides a better understanding of the thermal dynamics of ICs. Furthermore, it links the IC design with the BTS unit thermal optimization in early phase and provides accurate hot spot information for system level thermal solution dimensioning. Thus, this approach will help engineers make informed decisions and optimize the efficiency and reliability of their design at early phases of IC development.